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BOUNDARY-SCAN DESCRIPTION LANGUAGE (BSDL) Several data formats have emerged to make IEEE 1149.1 successful and well-supported by tools. This page discusses the most popular data format for describing how IEEE 1149.1 was implemented in a device -- BSDL, or Boundary Scan Description Language. Back to Specifications BOUNDARY-SCAN DESCRIPTION LANGUAGE (BSDL) - BRIEF DESCRIPTION In 1990, the IEEE 1149.1 standard was approved and implementation of the standard accelerated. As more people became aware of and used the standard, the need for a standard method for describing IEEE 1149.1-compatible devices was recognized. The IEEE 1149.1 working group established a subcommittee to develop a device description language to address this need. The subcommittee has since developed and approved an industry standard language called Boundary Scan Description Language (BSDL). BSDL is a subset of VHDL (VHSIC Hardware Description Language) that describes how IEEE 1149.1 is implemented in a device and how it operates. BSDL captures the essential features of any IEEE 1149.1 implementation. BSDL was approved in 1994 as IEEE Std. 1149.1b. The IEEE 1149.1 is a structured design-for-test approach well suited for tools and automation. Tools developed to support the standard can control the TAP (Test Access Port) if they know how the boundary scan architecture was implemented in the device. Tools can also control the I/O pins of the device. BSDL provides a standard machine and human-readable data format for describing how IEEE 1149.1 is implemented in a device. Back to top of page Back to Specifications HOW BSDL IS USED Many IEEE 1149.1 tools already on the market support BSDL as a data input format. These tools offer different capabilities to customers implementing IEEE 1149.1 into their designs including board interconnect Automatic Test Pattern Generation (ATPG) and Automatic Test Equipment (ATE). When you use tools that support BSDL you can often obtain BSDL from your semiconductor vendor. This can result in significant time and cost savings. Teradyne estimates that to create in-circuit test patterns for a leading microprocessor normally may require as much as seven weeks time:
If the microprocessor supports IEEE 1149.1, and the BSDL is supplied by the vendor, the time to develop in-circuit test patterns is less than two hours (less than $100) using today's tools. Back to top of BSDL description Back to top of page Back to Specifications ELEMENTS OF BSDL A BSDL description for a device consists of the following elements: ENTITY DESCRIPTIONS The entity statement names the entity, such as the device name (e.g., SN74ABT8245). An entity description begins with an entity statement and terminates with an end statement. entity XYZ is
{statements to describe the entity go here}
end XYZ
Back to top of BSDL elementsBack to top of BSDL description GENERIC PARAMETER A generic parameter is a parameter that may come from outside the entity, or it may be defaulted, such as a package type (e.g., "DW"). generic (PHYSICAL_PIN_MAP : string := "DW");Back to top of BSDL elements Back to top of BSDL description LOGICAL PORT DESCRIPTION The port description gives logical names to the I/O pins (system and TAP pins), and denotes their nature such as input, output, bidirectional, and so on. port (OE:in bit;
Y:out bit_vector(1 to 3);
A:in bit_vector(1 to 3);
GND, VCC, NC:linkage bit;
TDO:out bit;
TMS, TDI, TCK:in bit);
Back to top of BSDL elementsBack to top of BSDL description USE STATEMENTS The use statement refers to external definitions found in packages and package bodies. use STD_1149_1_1990.all;Back to top of BSDL elements Back to top of BSDL description PIN MAPPING(S) The pin mapping provides a mapping of logical signals onto the physical pins of a particular device package. attribute PIN_MAP of XYZ : entity is
PHYSICAL_PIN_MAP;
constant DW:PIN_MAP_STRING:=
"OE:1, Y:(2,3,4), A:(5,6,7), GND:8, VCC:9, "&
"TDO:10, TDI:11, TMS:12, TCK:13, NC:14";
Back
to top of BSDL elementsBack to top of BSDL description SCAN PORT IDENTIFICATION The scan port identification statements define the device's TAP. attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6,
BOTH);
Back to
top of BSDL elementsBack to top of BSDL description INSTRUCTION REGISTER DESCRIPTION The Instruction Register description identifies the device-dependent characteristics of the Instruction Register. attribute INSTRUCTION_LENGTH of XYZ : entity is 2;
attribute INSTRUCTION_OPCODE of XYZ : entity is
"BYPASS (11), "&
"EXTEST (00), "&
"SAMPLE (10) ";
attribute INSTRUCTION_CAPTURE of XYZ : entity is
"01";
Back to top of BSDL elementsBack to top of BSDL description REGISTER ACCESS DESCRIPTION The register access defines which register is placed between TDI and TDO for each instruction. attribute REGISTER_ACCESS of XYZ : entity is
"BOUNDARY (EXTEST, SAMPLE), "&
"BYPASS (BYPASS) ";
Back to top of BSDL elementsBack to top of BSDL description BOUNDARY REGISTER DESCRIPTION The Boundary Register description contains a list of boundary scan cells, along with information regarding the cell type and associated control. attribute BOUNDARY_LENGTH of XYZ : entity is 7;
attribute BOUNDARY_REGISTER of XYZ : entity is
"0 (BC_1, Y(1), output3, X, 6, 0, Z), "&
"1 (BC_1, Y(2), output3, X, 6, 0, Z), "&
"2 (BC_1, Y(3), output3, X, 6, 0, Z), "&
"3 (BC_1, A(1), input, X), "&
"4 (BC_1, A(2), input, X), "&
"5 (BC_1, A(3), input, X), "&
"6 (BC_1, OE, input, X), "&
"6 (BC_1, *, control, 0)";
Back to top of BSDL elementsBack to top of BSDL description HOW TO FIND VENDOR BSDL FILES Many silicon vendors provide a means to obtain electronic forms of the BSDL descriptions for their devices. Click here to see a list. Back to top of page Back to Specifications
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